In a semiconductor integrated circuit (IC), transistor structures are critical in the control of current flow. Transistors are formed on silicon, or similar semiconductor substrates. A transistor is usually formed with two heavily-doped, spaced apart regions of silicon, which are called a source and a drain. A gate structure is formed between the source and the drain, and operates to control the amount of electrical current which flows between the source and drain. When appropriate voltage is applied to the gate, an electrically conductive channel is formed under the gate, allowing current flow between the source and the drain. Transistor structures are electronically-coupled within an IC by a series of conductive interconnects and metal lines.
Part of the process of forming transistors involves the application of various layers of material. One such layer, an intermetal dielectric layer, is utilized as an insulator between the gate and metal interconnects/lines. Silicon dioxide is the most widely used insulating material in the fabrication of semiconductor ICs. However, borophosphosilicate glass (BPSG) has typically been preferred in the past for an intermetal dielectric insulating layer, due to BPSG's superior abilities to reflow at low temperatures and getter mobile species. However, BPSG has conventionally been plagued with unacceptable fixed electrical charge, thus causing problems when used in semiconductor devices.
It is desirable that low dielectric constant materials be used for an insulating layer between interconnects and conducting regions in an IC. The minimum physical value possible for a dielectric constant is that of air (i.e.,. the constant referred to as .epsilon..sub.o). All other dielectric constants referred to herein are relative dielectric constants with respect to that of air, .epsilon..sub.o. However, an insulating layer of air (i.e., an airgap) does not provide mechanical support for other layers within an IC structure. The relative dielectric constant for silicon dioxide, a common dielectric, is slightly less than four. The lower the dielectric constant, the lower the parasitic capacitance between interconnects and other conductive regions. Parasitic capacitance undesirably increases delay time and power consumption in an IC. Delay time is increased by operation of the time constant, RC, wherein R is the resistance and C is the capacitance of IC. The time constant of an IC is proportional to the time required to decrease current flow through the IC by half. In order to meet consumer demands for high speed, low power consumption ICs, parasitic capacitance must be decreased in an IC. As ICs are becoming more dense, parasitic capacitance is becomingly an increasingly significant problem.
For example, IC memories are becoming increasingly dense due to the demand for increased memory storage. A dynamic random access memory (DRAM) device comprises an arrangement of individual memory cells. Each memory cell includes a capacitor capable of holding data as an electrical charge and an access transistor for accessing the charge stored on the capacitor. Data can be either stored to the memory cells during a write mode, or data can be retrieved from the memory cells during a read mode. The data is transmitted on signal lines, referred to as bit lines, or digit lines, which are connected to input/output (I/O) lines through field-effect transistors (FETs) used as switching devices. Word lines are coupled to gates of the FETs for switching them ON/OFF as desired, which allows for reading/writing to a particular memory cell.
Conventional dynamic memories use memory cells fabricated as capacitors in an integrated circuit to store data. The pairs of digit lines are fabricated as metal or silicided/polycided polysilicon lines on the integrated circuit and are connected to the memory cells for transmitting data stored in the memory cells. Although unique fabrication techniques and processes have been developed to reduce the size of the memory cells and access circuitry, the physical spacing requirements for the array architecture create a barrier to maximizing the available die area. That is, the reductions in memory cell size cannot be fully exploited due to the capacitance between conductive digit lines, word lines, interconnects, gates, and other conductive regions. In particular, each individual digit line is highly capacitive, due to the large quantity of attached memory bits, the length of the line, and its proximity to other features. This capacitance dictates the design parameters of die circuitry. Furthermore, these problems have conventionally been compounded due to the use of digit line pairs for determining the logic of a memory cell.
In the past, open digit line array architecture was most commonly used for DRAM circuitry. Such architecture is characterized by a memory cell located at each intersection between a word line and a digit line, or digit line complement. This type of architecture increases the chip density. However, several problems prevent such architecture from meeting the needs of highly dense ICs. Such problems include coupling between digit lines and high internal noise. Coupling between adjacent digit lines is inversely proportional to their spacing. As devices become smaller and array density increases, the coupling problem becomes more pronounced.
Alternatively, a folded digit line architecture was designed to improve noise immunity of such devices. Folded digit line architecture is characterized by a memory cell located at every other digit line/word line intersection. This type of architecture does not provide the same degree of packing density seen in the open digit line architecture described above. Its packing density is about twenty-five-percent lower than in the open digit line architecture. However, noise immunity of the integrated circuit is improved using folded digit line architecture over the open digit line architecture.
A recent trend in fabricating integrated circuit memories includes twisting adjacent digit line pairs to improve signal-to-noise characteristics. However, such twisting is undesirable because it occupies valuable silicon area. As devices are becoming more dense, silicon area is becoming more scarce.
Another area in an IC in which parasitic capacitance is a problem is between polysilicon conductive gate structures and interconnect structures, which are, for example, formed over source/drain regions. The capacitance between these two types of conductive regions is often termed fringing capacitance. Previous attempts to minimize such capacitance have included etching an air gap between the gate and a sidewall structure and then forming an air gap cap over the gate and sidewall structure on the opposite side of the air gap. While this technique effectively decreases the dielectric constant of the material between the interconnect structure and the gate structure, such an air gap lacks mechanical strength.
A method for decreasing parasitic capacitance between interconnects and other conductive regions within an IC is needed to meet consumer demands for higher speed applications with lower power consumption. In particular, parasitic capacitance must be reduced between digit lines in a memory cell array. Furthermore, parasitic capacitance must be reduced between gate structures and conductive interconnects, without severely reducing the mechanical integrity of the IC.